MSP430 -Note on Timer_A

        Timers essential to almost all embedded applications. They generate a fixed period events. Timers replaces the delay loops which allows CPU to sleep.

         Watchdog timer can be found on all msp430 devices. If we enable the watchdog timer our program  keeps resetting itself. So we disable the watchdog timer and uses the Timer_A.

Timer_A

        Timer is a Asynchronous 16-bit timer/counter. It has a 16-bit timer/counter register, TAR increments or decrements with each rising edge of the clock signal. The timer can generate an interrupt when it overflows. TAR can be cleared by setting TACLR bit. It also clears the clock divider and count direction for up/down mode. The timer clock can be sourced from ACLK, SMCLK, or externally via TACLK or INCLK. The clock source is selected with the TASSELx bits. The selected clock source may be passed directly to the timer or divided by 2, 4, or 8, using the IDx bits. The timer clock divider is reset when TACLR is set.

TIMER_A Control Register

TASSELx  :  

    They are 8th and 9th bits of the register.These two bits select the source of the clock for the timer. 

IDx  :

     They are 6th and 7th bis of the register. These bits select the divider for the input clock.

MCx  :

TACLR  :

     Bit 2 of the register. This is Timer_A clear. Setting this bit resets TAR, the clock divider, and the count direction. The TACLR bit is automatically reset and is always read as zero.

TAIE  :

    Bit 1 of the register. This is Timer_A interrupt enable. Setting this bit enables TAIFG interrupt request.

TAIFG  :

    Bit 0 of the register. This is Timer_A interrupt flag. If this bit is set then interrupt is pending.